Highlights:

  • Broadcom uses a technique known as hybrid copper bonding to join the dies that are stacked vertically. It is created via a multi-step, intricate process that researchers are still honing.
  • Broadcom claims that XDSiP offers seven times the signal density of B2F, an earlier packaging variant.

Broadcom Inc. launched XDSiP, the latest chip packaging technology, that helps to develop processors by stacking numerous silicon dies on top of one another.

The abbreviation for eXtreme Dimension System in Package is XDSiP. Broadcom is promoting it as a means of producing data center chips with greater power. The technology will serve as the foundation for a future server CPU with 288 cores, according to one customer, Fujitsu Ltd.

The underlying technology of XDSiP is 3.5D packaging, a new chip manufacturing technique.

Many contemporary processors have several silicon dies, each of which is dedicated to a certain task. While one might be designed for general-purpose computations, the other might be optimized to run artificial intelligence models. A die is frequently included for auxiliary functions including data movement in and out of the chip.

Placing the dies that comprise a processor side by side atop an interposer—a base layer—is one method of connecting them. We refer to this method as 2.5D chip packaging. With the use of Broadcom’s XDSiP technology, a processor with more transistors can be made by positioning dies not just next to one another but also on top of one another.

Broadcom uses a technique known as hybrid copper bonding to join the dies that are stacked vertically. It is created via a multi-step, intricate process that researchers are still honing.

The procedure begins with the addition of copper structures to the uppermost layer of two dies. After that, one die is positioned on top of the other so that the copper structures of the two dies face each other directly. Finally, a single connector made of melted copper structures enables the flow of current and data between the dies.

The technology’s ability to facilitate faster data transfer between processing components is one of its advantages over previous methods. Broadcom claims that XDSiP offers seven times the signal density of B2F, an earlier packaging variant. Furthermore, its superior mechanical strength lowers the possibility that pressing on the chip would result in problems.

Up to 2,500 square millimeters of silicon are typically found in processors built using 2.5D technology. Broadcom claims that its XDSiP technology allows for the addition of over 6,000 square millimeters. This leads to faster processing rates.

“Broadcom’s 3.5D platform enables chip designers to pair the right fabrication processes for each component while shrinking the interposer and package size, leading to significant improvements in performance, efficiency and cost,” said Frank Ostojic, Senior Vice President and General Manager of Broadcom’s ASIC Products Division.

According to the corporation, over five 3.5D products are presently being developed for consumers. Six HBM modules, one die devoted to data input and output functions, and four computation dies make up Broadcom’s flagship offering. A common form of high-speed memory found in AI circuits is HBM.

One of the clients that has embraced the technology is Fujitsu, which is utilizing it as the foundation for their next server CPU, Monaka. It will have cache modules based on five-nanometer technology and 288 Arm cores manufactured using a two-nanometer process. The cache modules, which are positioned on an interposer, will support the cores.

Production shipments of XDSiP-based processors are anticipated to start in February 2026, according to Broadcom. In 2027, Fujitsu intends to introduce its Monaka chip.