Highlights:

  • Ventana envisions businesses implementing the Veyron V1 in everything from 5G networking devices to vehicles.
  • Due to its free availability, RISC-V allows chip manufacturers to avoid the fees involved with licensing a proprietary ISA from a company like Arm Ltd.

Ventana Micro Systems Inc. recently introduced the Veyron V1, a data center processor based on the open-source RISC-V instruction-set architecture.

Ventana asserts that the Veyron V1 is the first RISC-V processor to match the performance of the most used data center chips. Furthermore, the startup claims its silicon can be used in other areas. Ventana envisions businesses implementing the Veyron V1 in everything from 5G networking devices to vehicles.

Balaji Baktha, the founder, and CEO of Ventana, said, “Our vision of delivering the highest performance RISC-V CPUs is helping to reshape next generation high performance open hardware architectures. Today, we have a significant first-mover advantage by providing a platform that can allow customers to innovate and differentiate.”

Last September, Ventana launched from stealth mode with USD 38 million in funding. It develops chips using the RISC-V instruction-set architecture created in 2010 at the University of California, Berkeley. In recent years, the architecture has garnered substantial industrial traction.

A processor can only do a limited number of computing operations by default. Frequently, these operations are rather straightforward. However, the processor can try varied combinations to perform complex calculations.

The simple computing processes a chip mix and matches to carry out calculations are called instructions. Instruction-set architecture, or ISA, is the blueprint that engineers use to implement them. Additionally, the ISA specifies other technical specifics, such as the sorts of data a processor may process.

RISC-V is a pre-packaged ISA which chip design teams use to create the instructions for a new processor and establish its technical details. It is freely released under an open-source license. Due to its free availability, RISC-V allows chip manufacturers to avoid the fees involved with licensing a proprietary ISA from a company like Arm Ltd.

Ventana’s recent introduction of the Veyron V1 chip is the first of a series of RISC-V processors the company intends to launch. It contains 16 cores that can operate at a clock speed of 3.6 gigahertz. The onboard L3 cache of 48 megabytes supports the cores.

Ventana has equipped its chip with reliability enhancements and virtualization capabilities, allowing servers to work more effectively. In addition, the startup claims that the Veyron V1 contains features to protect against side-channel assaults.

A side-channel attack is a type of hacking campaign in which technical information about a chip, such as its power consumption, is exploited to find ways to send malware or steal data.

The Veyron V1 is implemented as a chiplet, according to Ventana. It is a compact computing module that can be integrated with other processors. For example, a business may design a processor that combines Veyron V1 cores with additional computing units such as artificial intelligence accelerators.

Ventana claims that numerous Veyron V1 chiplets can be joined to form a system-on-chip with up to 192 cores. According to the firm, its silicon can help corporations design new processors up to two years faster and at a 75% cheaper cost.